Timing closure is the process by which a logic design consisting of primitive elements such as combinatorial logic gates (and, or, not, nand, nor, etc.) and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements. Unlike in a computer program where there is no explicit delay to perform a calculation, logic circuits have intrinsic and well defined delays to propagate inputs to outputs. In simple cases, the user can compute the path delay between elements manually.
Designing high-performance very large-scale integration (VLSI) chips has become more challenging than ever due to nanometer effects and accelerating time-to-market cycles. Due to the interconnect delay dominance, a small routing change in the design can increase coupling capacitances on its neighboring paths and significantly increase their path delays.
In nanometer technologies, timing convergence and timing yield are two of the most critical design issues. Due to the high device density and complicated physical design effects, a small change in the design
for timing fixes can cause new timing violations and result in design iterations. With the accelerating
time-to-market cycles, timing convergence has become the main focus in the design flow. Processes in
nanometer technologies are difficult to control.
Process variations cause timing variations in manufactured chips, causing failures and chips not meeting the performance guaranteed by design specifications.
Because of the high design and manufacturing costs, a small percentage of the timing yield loss can turn
the design from a money-spinner into a profit-loser. Therefore, it is paramount to address the timing
convergence and timing yield issues.
Timing convergence and timing yield issues have been aggravated by the following four factors: 1)
technology scaling, 2) process variations, 3) deep pipelining, and 4) ever increasing clock frequency.
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The main steps of the design flow, which may be involved in this process, are logic synthesis, placement, clock-tree synthesis and routing. With present technologies all of them need to be timing-aware for a design to properly meet its timing requirements, but with technologies in the range of the micrometre only logic synthesis EDA tools had such a prerequisite.
- Expertise in fullchip and block level timing closure with MMMC.
- Signal Integrity(crosstalk delay, noise glitch) aware timing closure with OCV/AOCV.
- Extraction, timing model build and SSTA.