Our team of experienced design engineers, complemented by a group of mid-level engineers have worked on multiple aspects of the RTL design flow on chips used in the automotive, mobile, networking, multimedia and processor industries. The following schematic demonstrates how Mirafra’s expertise helps the pieces of the jigsaw fall into place.
Register Transfer Level (RTL) simulation and verification is one of the initial steps that was done. This step ensures that the design is logically correct and without major timing errors. It is advantageous to perform this step, especially in the early stages of the design, because long synthesis and place-and-route times can be avoided when an error is discovered at this stage. This step also eliminates all the syntax errors from your VHDL code.
We used the Synopsys simulation tools to perform RTL verification. More specifically, vhdlan, or VHDL_analyzer was used. In addition, if the design contains LogiBloX components, (which is usually the case), the corresponding VHDL primitives generated by Xilinx tools along with Xilinx libraries have to be visible to the Synopsys tools.
Expertise in Front-end RTL design and SoC integration of multi-million gates IPs and SoCs for a variety of industry verticals like mobile, processors, networking and multimedia. Experience in the design verification involving standardized methodology like UVM based functional and formal techniques, VIP development, Equivalence checking and Gate level simulations of complex IP and SoC designs.
AIML’s verification team has proven expertise on taking complete ownership of verification of a design from scratch – whether that is an IP/SOC/subsystem – and taking it to verification closure by performing the following activities.
- Understanding the design specification document and creating the test plan.
- Creating the complete verification environment using industry standard methodologies like UVM/OVM/VMM.
- Executing the test plan by using an intelligent mix of constraint random, directed and random test cases Gate level simulations.
- Verification closure through corner case verification, coverage closure and regression closure.