Gate level simulation overcomes the limitations of static-timing analysis and is increasing being used due to low power issues, complex timing checks at 40nm and below, design for test (DFT) insertion at gate level and low power considerations. For DFT, scan chains are inserted after the gate-level netlist is created; gate level simulation is often used to determine whether scan chains are correct. Technology libraries at 45nm and below have far more timing checks and complex timing checks than older process nodes. Gate level simulation may take up to one-third of the simulation time and could potentially take most of the debugging time. It is run after RTL code is simulated and synthesized into a gate-level netlist. It requires a complete reset of the design.

Gate level simulation is used to boost the confidence regarding implementation of a design and can help verify dynamic circuit behaviour, which cannot be verified accurately by static methods. It is a significant step in the verification process.

There are many reasons for running gate level simulation, some of which are given below:
1. To give confidence in verification of low-power structures, absent in RTL and added during synthesis. It is a probable method to catch multi-cycle paths if tests exercising these are available. Power estimation is done on the netlist for power numbers.
2. To verify the power-up and reset operation of the design and to check if the design has any unintentional dependencies on initial conditions.
3. To verify DFT structures absent in RTL and added during or after synthesis. Scan chains are generally inserted after the gate-level netlist has been created. Hence, gate level simulation is often used to determine whether scan chains are correct. It is also required to simulate ATPG patterns.